Optimal multilevel interconnect architecture aspect ratios for GSoCs

Author

Venkatesan, Raguraman ; Davis, Jeffrey A. ; Meindl, James D.

Author_Institution

Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA

fYear

2003

fDate

17-20 Sept. 2003

Firstpage

17

Lastpage

20

Abstract

A methodology for optimal design of the reverse-scaled interconnect stack is used to optimize the interconnect cross-sectional aspect ratios to increase performance or reduce area. For a 100 nm generation macrocell in a GSI system-on-a-chip (GSoC), using an optimal aspect ratio is demonstrated to achieve 40% increase in clock frequency or 53% decrease in macrocell area. The effects of inductance and repeater insertion on the optimum aspect ratio are illustrated using a case study from the 45 nm technology generation. Comparison with a commercial 130 nm process generation shows good matching with the model predictions for the aspect ratios of the upper metal levels, while recommendations are suggested for a better design of the lower metal levels.

Keywords

ULSI; circuit optimisation; integrated circuit design; integrated circuit interconnections; system-on-chip; 100 nm; 130 nm; 45 nm; GSI system-on-a-chip; GSoC; SoC; clock frequency increase; gigascale integration; inductance; interconnect cross-sectional aspect ratio optimization; interconnect cross-sectional dimensions; lower metal levels; macrocell area reduction; multilevel interconnect architecture; repeater insertion; reverse-scaled interconnect stack; upper metal levels; Application specific integrated circuits; Clocks; Crosstalk; Delay; Frequency; Macrocell networks; Optimization methods; Power system interconnection; Wire; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

SOC Conference, 2003. Proceedings. IEEE International [Systems-on-Chip]

Print_ISBN

0-7803-8182-3

Type

conf

DOI

10.1109/SOC.2003.1241453

Filename

1241453