Abstract :
In SoC design, several system level architectural alternatives may be explored if the custom-logic blocks (CLB) in the system could be readily tuned to meet different constraints imposed by each candidate system architecture. A set of RTL designs, each distinct in terms of major cycles required, operation schedule, and resource utilization, may be generated using high-level synthesis for each CLB. The designer, however must ascertain that these RTLs are equivalent. We present a novel RTL technique to establish such equivalence regardless of the high-level synthesis methods and constraints, enabling SoC architecture exploration.
Keywords :
formal verification; logic design; system-on-chip; CLB constraints; RT level verification method; RTL behavioral equivalence checking; RTL design; SoC architecture exploration; SoC design; custom-logic blocks; high-level synthesis; operation schedule; required cycles; resource utilization; system level architectural alternatives; Algorithm design and analysis; Circuits; Design methodology; Electronic design automation and methodology; Hardware; High level synthesis; Job shop scheduling; Laboratories; Resource management; System-on-a-chip;
