Title :
Digital signal processing at 1 GHz in a field-programmable object array
Author_Institution :
MathStar, Inc., Minneapolis, MN, USA
Abstract :
Autonomous MAC and ALU processors and register files (three types of silicon objects) are implemented with custom logic to achieve 1 GHz operation. Arraying hundreds of objects in parallel in a single chip enables high DSP performance from an in-circuit reprogrammable architecture. For example, a 1024-point radix-2 FFT with (16+16)-bit complex samples can be completed every 160 ns using 64 butterflies (128 MAC, 128 ALU, and 64 RF objects) assisted by 128 ALU and 64 RF objects for inter-stage data routing.
Keywords :
digital signal processing chips; logic design; multiprocessing systems; multiprocessor interconnection networks; parallel architectures; programmable logic arrays; 1 GHz; 160 ns; DSP; FPOA; autonomous ALU processors; autonomous MAC processors; autonomous register files; butterflies; digital signal processing; field-programmable object array; in-circuit reprogrammable architecture; inter-stage data routing; parallel architecture; radix-2 FFT complex samples; silicon object communication; Clocks; Communication system control; Digital signal processing; Integrated circuit interconnections; LAN interconnection; Logic arrays; Radio frequency; Registers; Silicon; Synchronization;
Conference_Titel :
SOC Conference, 2003. Proceedings. IEEE International [Systems-on-Chip]
Print_ISBN :
0-7803-8182-3
DOI :
10.1109/SOC.2003.1241462
