Design and implementation of a scalable multimedia processor

Author

Dassatti, Alberto ; Martina, Maurizio ; Masera, Guido ; Molino, A. ; Piccinini, Gianluca ; Vacca, Fabrizio ; Zamboni, Maurizio

Author_Institution

Dipt. di Elettronica, Politecnico di Torino, Italy

fYear

2003

fDate

17-20 Sept. 2003

Firstpage

89

Lastpage

92

Abstract

This work describes the design and implementation of a highly customisable multimedia processor. The proposed core has been developed with the goal of simplicity and effectiveness. Moreover, thanks to its soft-core nature, it is suited for being implemented over different physical layers. In particular, in this paper, an FPGA-oriented implementation is addressed. Additionally, this core can be configured to contain a different number of functional units depending on the specific application. In order to validate the proposed approach, three different configuration profiles have been fully implemented on a Xilinx Virtex XCV2000E FPGA.

Keywords

field programmable gate arrays; logic design; microprocessor chips; multimedia computing; parallel architectures; FPGA implementation; VLIW configuration; highly customisable multimedia processor; scalable multimedia processor; soft processor core; very long instruction word architectures; Communication system control; Computer architecture; Digital signal processing; Field programmable gate arrays; Hardware; Parallel processing; Physical layer; Pipelines; Registers; VLIW;

fLanguage

English

Publisher

ieee

Conference_Titel

SOC Conference, 2003. Proceedings. IEEE International [Systems-on-Chip]

Print_ISBN

0-7803-8182-3

Type

conf

DOI

10.1109/SOC.2003.1241469

Filename

1241469