Title :
Module generator of data recovery for serial link receiver
Author :
Jou, Shyh-Jye ; Lin, Chih-Hsien ; Chen, Yen-Hung ; Li, Zheng-Hong
Author_Institution :
Dept. of Electr. Eng., Nat. Central Univ., Chung-li, Taiwan
Abstract :
A module generator for the all-digital data recovery of a highspeed serial link, using an oversampling method, is proposed. The architecture of the proposed method is very regular and hence very suitable for standard cell implementation flow, which also makes it very suitable as a soft silicon intellectual property. This module generator can automatically generate the design parameters to deal with the oversampling architecture to meet different specifications. A design example, generated by the module generator, is implemented by using the TSMC 0.35 μm 1P4M cell library. The maximum performance of the design (without extra pipelining stages) can reach 2.09 Gbps with power consumption of 112.2 mW at 3.3 V.
Keywords :
data communication equipment; integrated circuit design; logic design; receivers; signal sampling; telecommunication links; 0.35 micron; 112.2 mW; 2.09 Gbit/s; 3.3 V; all-digital data recovery module generator; communication serial links; data transmission; feedforward oversampling method; high-speed serial link receiver; soft silicon intellectual property; standard cell implementation flow; Application software; Bandwidth; Clocks; Computer networks; Feedforward systems; Frequency synchronization; Intellectual property; Silicon; Timing; Transceivers;
Conference_Titel :
SOC Conference, 2003. Proceedings. IEEE International [Systems-on-Chip]
Print_ISBN :
0-7803-8182-3
DOI :
10.1109/SOC.2003.1241470
