Quantum mechanical effects on CMOS SOC performance

Author

Wang, Lihui ; Chen, Qiang ; Murali, Raghunath ; Meindl, James D.

Author_Institution

Microelectron. Res. Center, Georgia Inst. of Technol., Atlanta, GA, USA

fYear

2003

fDate

17-20 Sept. 2003

Firstpage

109

Lastpage

112

Abstract

Comprehensively quantum mechanical effects and their impact on SOC CMOS logic circuit performance are studied, based on novel compact physical models. Significant performance degradation and power dissipation increase due to quantum mechanical effects are demonstrated in sub-100nm technologies. Specifically, 39% and 41% increase in power dissipation and device area, respectively, due to quantum effects compared with classical performance, are projected for the 25 nm technology generation. The results show that quantum effects will become a key constraint on circuit performance in future SOC technology generations.

Keywords

CMOS logic circuits; circuit simulation; integrated circuit modelling; quantum theory; semiconductor device models; system-on-chip; 25 nm; CMOS SOC performance; CMOS logic circuits; MOSFET current-voltage characteristic model; compact physical models; performance degradation; power dissipation increase; quantum mechanical effects; CMOS technology; Circuits; Delay estimation; Electrons; Energy states; Potential well; Quantization; Quantum mechanics; Semiconductor device modeling; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

SOC Conference, 2003. Proceedings. IEEE International [Systems-on-Chip]

Print_ISBN

0-7803-8182-3

Type

conf

DOI

10.1109/SOC.2003.1241473

Filename

1241473