A leakage-tolerant high fan-in dynamic circuit design style [logic circuits]

Author

Mahmoodi-Meimand, Hamid ; Roy, Kaushk

Author_Institution

Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA

fYear

2003

fDate

17-20 Sept. 2003

Firstpage

117

Lastpage

120

Abstract

A leakage-tolerant design technique for high fan-in dynamic logic circuits is presented. An NMOS transistor with gate and drain terminals tied together (diode) is added in series with the evaluation network of standard domino circuits. Due to the stacking effect, the leakage of the evaluation path significantly decreases, thereby improving the robustness of the circuit against deep-submicron subthreshold leakage and input noise. To improve the speed of the circuit, a current mirror is also employed in the evaluation network to increase the evaluation current. The proposed technique (diode-footed domino) exhibits considerable improvement in leakage and noise-immunity as compared to the standard domino circuits. Simulation results of wide fan-in gates designed using Berkeley predictive technology modes of 70 nm technology demonstrate at least 1.9× noise-immunity improvement at the same delay compared to the standard domino circuits.

Keywords

current mirrors; integrated circuit design; integrated circuit noise; leakage currents; logic circuits; logic design; logic simulation; 70 nm; current mirror; deep-submicron subthreshold leakage; diode-footed domino circuits; high fan-in dynamic logic circuits; input noise; leakage-tolerant logic circuits; noise-immunity improvement; stacking effect; tied gate/drain terminal NMOS transistor; Circuit noise; Circuit synthesis; Diodes; Logic circuits; MOSFETs; Mirrors; Noise robustness; Predictive models; Stacking; Subthreshold current;

fLanguage

English

Publisher

ieee

Conference_Titel

SOC Conference, 2003. Proceedings. IEEE International [Systems-on-Chip]

Print_ISBN

0-7803-8182-3

Type

conf

DOI

10.1109/SOC.2003.1241475

Filename

1241475