Co-processor architecture for MPEG-4 main profile visual compositing

Author

Berekovic, M. ; Pirsch, P. ; Selinger, T. ; Wels, K.-I. ; Miro, C. ; Lafage, A. ; Heer, C. ; Ghigo, G.

Author_Institution

Lab. fur Informationstechnol., Hannover Univ., Germany

Volume

2

fYear

2000

fDate

2000

Firstpage

180

Abstract

The TANGRAM VLSI co-processor is intended to assist existing MPEG-4 video-decoders to perform the computation intensive final step of MPEG-4 video decoding: compositing of scenes at the display. TANGRAM consists of a RISC control processor and multiple powerful arithmetic units that perform rendering calculations directly in hardware. This hybrid architecture enables adaptation to changes in algorithms or support for different video-formats in software. Communication to a host CPU and video decoding hardware is done via the very common PI-bus on-chip interface. TANGRAM directly interfaces with the ITU-R601/656 digital video output. VHDL implementation and synthesis for a 0.35 μ standard-cell library provide an estimate of 100 MHz achievable clock-frequency (worst-case), 52 mm² overall area and 1 Watt power dissipation. TANGRAM has sufficient performance for rendering of MPEG-4 Main Profile@Layer3 scenes (CCIR)

Keywords

VLSI; coprocessors; decoding; digital arithmetic; hardware description languages; reduced instruction set computing; video signal processing; 0.35 micron; 1 W; 100 MHz; ITU-R601/656 digital video output; MPEG-4; Main Profile@Layer3 scenes; PI-bus on-chip interface; RISC control processor; TANGRAM VLSI co-processor; VHDL implementation; achievable clock-frequency; main profile visual compositing; multiple powerful arithmetic units; power dissipation; rendering calculations; scene compositing; standard-cell library; video decoding; Computer architecture; Computer displays; Coprocessors; Decoding; Hardware; Layout; MPEG 4 Standard; Reduced instruction set computing; Rendering (computer graphics); Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on

Conference_Location

Geneva

Print_ISBN

0-7803-5482-6

Type

conf

DOI

10.1109/ISCAS.2000.856288

Filename

856288