Title :
Impact of on-chip process variations performance on MCML [MOS current mode logic]
Author_Institution :
Philips EDT, Netherlands
Abstract :
The effect of on-chip process variations on MOS current mode logic (MCML) performance is explored. A closed form expression for the noise-margin is derived. On-chip process variations are shown to set the lower limit for the power dissipation of an MCML family.
Keywords :
MOS logic circuits; current-mode logic; integrated circuit modelling; integrated circuit noise; logic simulation; MCML on-chip process variations; MCML power dissipation lower limit; MOS current mode logic performance; noise-margin; Circuit noise; Coupling circuits; Crosstalk; Delay; Logic circuits; Noise generators; Noise reduction; Power dissipation; Power supplies; Voltage;
Conference_Titel :
SOC Conference, 2003. Proceedings. IEEE International [Systems-on-Chip]
Print_ISBN :
0-7803-8182-3
DOI :
10.1109/SOC.2003.1241479
