DocumentCode
2230684
Title
A low power design approach for MOS current mode logic
Author
Ismail, Ayman H. ; Elmasry, Mohamed I.
Author_Institution
VLSI Res. Group, Univ. of Waterloo, Ontario, Canada
fYear
2003
fDate
17-20 Sept. 2003
Firstpage
143
Lastpage
146
Abstract
In this paper, a closed form expression for the propagation delay of MOS current mode logic (MCML) is derived using simplified BSIM transistor equations. The expression shows the parameters that affect the delay. Based on the obtained expression, a design approach is devised that leads to minimum power dissipation in MOS current mode logic gates for a given gate delay and load. This approach can serve as the basis for an automated methodology to size power efficient MCML gates that are extensively used in integrated optical transceivers.
Keywords
MOS logic circuits; current-mode logic; integrated circuit design; logic design; logic simulation; low-power electronics; MCML propagation delay; MOS current mode logic; integrated optical transceivers; logic gate sizing; low power design; minimum logic gate power dissipation; CMOS logic circuits; High speed optical techniques; Integrated optics; Inverters; Logic circuits; Logic design; Power dissipation; Propagation delay; Transceivers; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
SOC Conference, 2003. Proceedings. IEEE International [Systems-on-Chip]
Print_ISBN
0-7803-8182-3
Type
conf
DOI
10.1109/SOC.2003.1241480
Filename
1241480
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