DocumentCode :
2230699
Title :
Efficient partial enumeration for timing analysis of asynchronous systems
Author :
Verlind, Eric ; deJong, G. ; Lin, Bill
Author_Institution :
IMEC, Leuven, Belgium
fYear :
1996
fDate :
3-7 Jun, 1996
Firstpage :
55
Lastpage :
58
Abstract :
This paper presents an efficient method for the timing verification of concurrent systems, modeled as labeled Timed Petri nets. The verification problems we consider require us to analyze the system´s reachable behaviors under the specified time delays. Our geometric timing analysis algorithm improves over existing ones by enumerating the state space only partially. The algorithm relies on a concept called pre-mature firing and a new, extended notion of clocks with a negative age. We have tested the fully automated procedure on a number of examples. Experimental results obtained on highly concurrent Petri nets with more than 6000 nodes and 10210 reachable states show that the proposed method can drastically reduce computational cost
Keywords :
Petri nets; asynchronous circuits; formal verification; logic CAD; timing; asynchronous systems; clocks; computational cost; concurrent systems; efficient partial enumeration; geometric timing analysis algorithm; highly concurrent Petri nets; labeled timed Petri nets; pre-mature firing; reachable behaviors; state space; timing analysis; timing verification; Automatic testing; Circuits; Clocks; Concurrent computing; Delay effects; Design methodology; Permission; Petri nets; State-space methods; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference Proceedings 1996, 33rd
Conference_Location :
Las Vegas, NV
ISSN :
0738-100X
Print_ISBN :
0-7803-3294-6
Type :
conf
DOI :
10.1109/DAC.1996.545545
Filename :
545545
Link To Document :
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