Clocking for correct functionality on wave pipelined circuits

Wave pipelining is a method of speeding up the circuit design without the insertion of registers. This reduces the overhead related to clocking significantly and allows for better temporal logic utilization. However, because of the fact there are no intermediate registers, the clocking of wave pipelined circuits becomes more delicate and very susceptible to delay changes due to process, voltage and temperature (PVT) variations. With the traditional method of pipelining, it becomes just a problem of frequency adjustment, but, with wave pipelining, it becomes a more difficult problem due to more complicated constraints involving clock frequency and skew. In this paper, we look at some of the prior works done in this area, and introduce a localized clock circuitry scheme to address this issue.