Fast and energy-efficient asynchronous level converters for multi-VDD design [CMOS ICs]

Multi-VDD design effectively reduces power consumption but the need for level conversion imposes delay and energy penalties, limiting the potential gains. In this work, we describe new level converting circuits that consume 8-50% less energy at equivalent or better speeds compared to those available in the literature. We suggest that level converters should be evaluated largely by maximum speed as slower level converters waste valuable timing slack that can be used to reduce total system energy. Based on this metric, the new structures offer up to 17% faster operation than conventional designs. We also propose embedding functionality into level converters. For typical values of the low VDD, this technique can reduce delay by 15% at constant energy or lower energy by up to 30% at fixed delay.