Title :
Compiler optimizations in the PACT HDL behavioral synthesis tool for ASICs and FPGAs
Author :
Tang, Xiaoyong ; Jiang, Tianyi ; Jones, Alex ; Banerjee, Prith
Author_Institution :
Dept. of Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
Abstract :
This paper describes the PACT HDL compiler, which allows users to develop algorithms in C and synthesize hardware designs onto FPGAs and ASICs. It also explicitly addresses low power issues during the high-level synthesis stages. Several power-saving compiler optimizations are discussed.
Keywords :
C language; application specific integrated circuits; circuit optimisation; field programmable gate arrays; hardware description languages; high level synthesis; low-power electronics; ASIC; C algorithms; FPGA; PACT HDL behavioral synthesis tool; hardware synthesis; low power high-level synthesis; power-saving compiler optimizations; Algorithm design and analysis; Application specific integrated circuits; Field programmable gate arrays; Flow graphs; Hardware design languages; High level languages; High level synthesis; Optimizing compilers; Program processors; System-on-a-chip;
Conference_Titel :
SOC Conference, 2003. Proceedings. IEEE International [Systems-on-Chip]
Print_ISBN :
0-7803-8182-3
DOI :
10.1109/SOC.2003.1241490
