Title :
Tile-based power planning during floorplanning
Author :
Fang, Jyh Pern ; Chen, Sao Jie
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
In this paper, we introduce a tile-based approach to power planning at the stage of floorplanning. For a given floorplan solution, an associated tile graph of power density is generated, and the temperature of the floorplan is evaluated tile by tile. In contrast to the direct evaluation from the power consumption of circuit blocks and neglecting the effect of heat diffusion, we take the effect of heat diffusion in a die into consideration. Also, we simplify the computing of temperature by way of a tile graph, which make the heat estimation and thus the power planning in the floorplanning stage possible.
Keywords :
integrated circuit layout; thermal analysis; thermal diffusion; thermal management (packaging); die heat diffusion; floorplanning; heat estimation; hot spots; power density tile graph; temperature computation; thermal analysis; tile-based power planning; Bismuth; Circuits; Clocks; Energy consumption; Piecewise linear approximation; Power engineering and energy; Power generation; Temperature; Tiles; Very large scale integration;
Conference_Titel :
SOC Conference, 2003. Proceedings. IEEE International [Systems-on-Chip]
Print_ISBN :
0-7803-8182-3
DOI :
10.1109/SOC.2003.1241491
