Title :
Verification of asynchronous circuits using time Petri net unfolding
Author :
Semenov, Alexei ; Yakovlev, Alexandre
Author_Institution :
Dept. of Comput. Sci., Newcastle upon Tyne Univ., UK
Abstract :
This paper describes a novel approach to timing analysis and verification of asynchronous circuits with bounded delays. The method is based on the time-driven unfolding of a time Petri net model of a circuit. Each reachable state, together with its timing constraints is represented implicitly. Our method is used to verify freedom from hazards in asynchronous circuits consisting of micropipeline components and logic gates
Keywords :
Petri nets; asynchronous circuits; formal verification; logic CAD; reachability analysis; timing; asynchronous circuit verification; bounded delays; logic gates; micropipeline components; reachable state; time Petri net unfolding; time-driven unfolding; timing analysis; Asynchronous circuits; Delay; Hazards; Iterative algorithms; Logic circuits; Logic gates; Permission; Process design; Switching circuits; Timing;
Conference_Titel :
Design Automation Conference Proceedings 1996, 33rd
Conference_Location :
Las Vegas, NV
Print_ISBN :
0-7803-3294-6
DOI :
10.1109/DAC.1996.545546
