A 3.3 V, 1.6 GHz, low-jitter, self-correcting DLL based clock synthesizer in 0.5 μm CMOS

Author

Foley, David J. ; Flynn, Michael P.

Author_Institution

Nat. Microelectron. Res. Centre, Univ. Coll. Cork, Ireland

Volume

2

fYear

2000

fDate

2000

Firstpage

249

Abstract

This paper describes a 1.6 GHz clock synthesizer which employs a delay locked loop (DLL) to generate multiple phases that are combined to produce the desired output clock frequency. A self correcting circuit ensures that the DLL arrives at the correct locked state irrespective of its power-up state or following either a wide variation in the input reference clock frequency or missing pulses in this clock signal. The measured edge peak-to-peak and r.m.s. jitter for a 1.6 GHz output clock was 20 ps and 3.1 ps respectively. The circuit is powered from a 3.3 V supply and was fabricated on a 0.5 μm generic digital CMOS process

Keywords

CMOS digital integrated circuits; clocks; delay lock loops; high-speed integrated circuits; pulse generators; timing circuits; timing jitter; 0.5 micron; 1.6 GHz; 3.3 V; clock synthesizer; delay locked loop; digital CMOS process; low jitter; multiple phases generation; self-correcting DLL; Capacitors; Circuits; Clocks; Delay lines; Filters; Frequency; Phase locked loops; Synthesizers; Voltage control; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on

Conference_Location

Geneva

Print_ISBN

0-7803-5482-6

Type

conf

DOI

10.1109/ISCAS.2000.856308

Filename

856308