A clock extraction circuit using passive components-free filter in standard digital process

The necessity of passive components in analog circuit design such as Clock Recovery Circuits (CRC) or Phase Locked Loops (PLL) has been a main barrier to overcome especially when using a standard digital CMOS process. In addition to lack of support of high quality passives in digital CMOS, use of passive devices causes problems with area, thermal noise of resistance, process variation, mismatch of capacitances, and inability to scalable designs. Consequently current high speed clock recovery circuits are implemented mostly in bipolar technology or other passive friendly technology. However, these technologies are not well-suited to the higher levels of integration needed for “systems on a chip”. Also, current technology emphasis is shifting from increasing the operation speed of components to reducing their size, power consumption, and cost to eliminating the need for adjustment and trimming. These goals can be achieved by using fully passive component-free monolithic CMOS circuits. In this paper, we present a method for implementing a passive component filter which can be used in clock recovery circuit or PLLs