Title :
Area minimization of clock distribution networks using local topology modification
Author :
Saaied, H. ; Al-Khalili, D. ; Al-Khalili, A.J.
Author_Institution :
Concordia Univ., Montreal, Que., Canada
Abstract :
The quality of the clock distribution networks (CDNs) impacts the performance of an SoC. In this paper, we propose local topology modification (LTM) in order to enhance the CDN´s quality in terms of total wire length and wire elongations. The incorporation of this method into a deferred-merge embedding algorithm (DME) and greedy-DME (GDME) reduces the total wire length by around 7.83% and 9.77% respectively, with a slight increase in run time. In addition, we show that GDME relies intensively on wire elongations and it offers a solution that suffers from high standard deviation of the path lengths between clock pins and the CDN´s root (SDPL). Applying LTM to GDME reduces wire elongations and SDPL by 96.4 % and 51.5 % respectively.
Keywords :
circuit optimisation; clocks; integrated circuit layout; network topology; system-on-chip; CDN; GDME; LTM; SDPL; SoC; area minimization; clock distribution networks; deferred-merge embedding algorithm; greedy-DME; local topology modification; wire elongations; wire length reduction; Capacitance; Clocks; Delay; Educational institutions; Network topology; Peak to average power ratio; Pins; Power dissipation; System performance; Wire;
Conference_Titel :
SOC Conference, 2003. Proceedings. IEEE International [Systems-on-Chip]
Print_ISBN :
0-7803-8182-3
DOI :
10.1109/SOC.2003.1241498
