DocumentCode
2231149
Title
A 1.4V 10b CMOS DC DAC in 0.01mm2
Author
Greenley, Brandon R. ; Veith, Raymond L. ; Chang, Dong-Young ; Moon, Un-Ku
Author_Institution
Tektronix Inc., Beaverton, OR, USA
fYear
2003
fDate
17-20 Sept. 2003
Firstpage
237
Lastpage
238
Abstract
A low voltage 10 bit DC DAC is fabricated in a standard 0.18 μm CMOS process. The DAC is optimized for circuit calibration in large ASICs and occupies 0.01034 mm2 (110 μm×94 μm) of die area. Creative layout and current mirroring techniques are implemented to minimize area while providing output current with sufficient headroom. The measured DNL/INL is better than 0.7/0.75 LSB and 0.8/2 LSB for 1.8 V and 1.4 V power supplies, respectively. The DAC consumes 3.96 mW at 1.8 V and 3.08 mW at 1.4 V.
Keywords
CMOS integrated circuits; application specific integrated circuits; calibration; circuit optimisation; current mirrors; digital-analogue conversion; integrated circuit design; low-power electronics; mixed analogue-digital integrated circuits; 0.18 micron; 1.4 V; 1.8 V; 110 micron; 3.08 mW; 3.96 mW; 94 micron; ASIC circuit calibration; CMOS DC DAC; DNL/INL; area efficient calibration circuits; area minimization; current mirroring techniques; low voltage DAC; mixed-signal ASIC; CMOS process; Calibration; Circuits; Equations; Instruments; Mathematical model; Power measurement; Power supplies; Resistors; Semiconductor device measurement;
fLanguage
English
Publisher
ieee
Conference_Titel
SOC Conference, 2003. Proceedings. IEEE International [Systems-on-Chip]
Print_ISBN
0-7803-8182-3
Type
conf
DOI
10.1109/SOC.2003.1241500
Filename
1241500
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