DocumentCode
2231276
Title
An integrated optimization strategy for saving energy on multiprocessor-on-a-chip architectures
Author
Chen, G. ; Kandemir, Mahmut ; Kolcu, I.
Author_Institution
Dept. of Comput. & Sci. Eng., Pennsylvania State Univ., University Park, PA, USA
fYear
2003
fDate
17-20 Sept. 2003
Firstpage
253
Lastpage
254
Abstract
In an on-chip multiprocessor, there exist two major ways of saving energy: voltage scaling and processor shut-down. This paper makes a case for an integrated strategy where these two techniques are applied in concert for the best energy savings. We present an integer linear programming (ILP) approach that selects the best combination of voltage scaling and processor shut-down.
Keywords
integer programming; linear programming; logic design; low-power electronics; multiprocessing systems; optimisation; ILP; MPoC architecture; MPoC energy saving; code profiling; integer linear programming; integrated optimization strategy; multiprocessor-on-a-chip architecture; processor shut-down; voltage scaling; Banking; Computer architecture; Dynamic voltage scaling; Energy consumption; Frequency; Hardware; Hip; Integer linear programming; Linear programming; USA Councils;
fLanguage
English
Publisher
ieee
Conference_Titel
SOC Conference, 2003. Proceedings. IEEE International [Systems-on-Chip]
Print_ISBN
0-7803-8182-3
Type
conf
DOI
10.1109/SOC.2003.1241507
Filename
1241507
Link To Document