Title :
Dual-monotonic domino gate mapping and optimal output phase assignment of domino logic
Author :
Zhao, Min ; Sapatnekar, Sachin S.
Author_Institution :
Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, MN, USA
Abstract :
In this paper two problems on domino logic synthesis are addressed. A mapping method that maps the complementary logic cones independently when AND/OR logic is to be implemented and together using dual-monotonic gates in the case of XOR/XNOR logic, is proposed. The results show up to 28.9% improvement in area and always show the same or better performance in delay over existing approaches. Then a 0-1 integer programming formulation is provided for the output phase assignment problem for domino logic. It considers the cost difference between two polarities and enables a standard linear programming package to be used to solve the problem. The results show up to 41.0% improvement in area
Keywords :
circuit CAD; integer programming; integrated circuit design; integrated logic circuits; linear programming; logic CAD; logic gates; 0-1 integer programming formulation; AND/OR logic implementation; XOR/XNOR logic implementation; complementary logic cones; domino logic synthesis; dual-monotonic domino gate mapping; optimal output phase assignment; standard linear programming package; Costs; Delay; Linear programming; Logic circuits; Logic design; Logic gates; Logic programming; Network synthesis; Signal mapping; Signal synthesis;
Conference_Titel :
Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on
Conference_Location :
Geneva
Print_ISBN :
0-7803-5482-6
DOI :
10.1109/ISCAS.2000.856323
