Implementation of high-speed blind channel equalizer for QAM modems

Author

Park, Weon H. ; Hong, J.H. ; Sunwoo, Myung H. ; Kim, Kyung H. ; Oh, Sung K.

Author_Institution

Sch. of Electr. & Comput. Eng., Ajou Univ., Suwon, South Korea

fYear

2003

fDate

17-20 Sept. 2003

Firstpage

263

Lastpage

264

Abstract

This paper proposes a decision feedback equalizer (DFE) with an error feedback filter using the multi-modulus algorithm (MMA). The proposed equalizer has been designed for 64/256 QAM modulations. The proposed DFE adds the error feedback filter to the DFE structure to improve the channel adaptive performance. We have simulated the proposed equalizers using the Cadence® SPW™ CAD tool. The architecture has been modeled by VHDL and logic synthesis has been performed using the 0.25 μm Faraday library. The total gate count of the proposed equalizer is about 190,000 and the operating frequency is 15 MHz. The proposed equalizers provide a symbol rate up to 64 Mbps.

Keywords

blind equalisers; decision feedback equalisers; hardware description languages; logic design; logic simulation; modems; quadrature amplitude modulation; 0.25 micron; 15 MHz; 64 Mbit/s; 64/256 QAM modulations; DFE; MMA; QAM modems; VHDL; channel adaptive performance; decision feedback equalizer; error feedback filter; high-speed blind channel equalizer; multi-modulus algorithm; symbol rate; Adaptive filters; Constellation diagram; Decision feedback equalizers; Delay; Equations; Least squares approximation; Modems; Quadrature amplitude modulation; Telecommunication computing; Transversal filters;

fLanguage

English

Publisher

ieee

Conference_Titel

SOC Conference, 2003. Proceedings. IEEE International [Systems-on-Chip]

Print_ISBN

0-7803-8182-3

Type

conf

DOI

10.1109/SOC.2003.1241512

Filename

1241512