Low complexity VLSI implementation of a joint successive interference cancellation with interleaving scheme

The performance of wideband code division multiple access (WCDMA) can be severely degraded as the number of users increases due to the increase in interference. Multi-user detection is a scheme, which can cancel the interference generated by other users and hence can improve the system capacity. Recently a joint successive interference cancellation with interleaving (JSICI) scheme has been proposed for multi-user detection. However the complexity of the scheme is very high. In this paper, we propose a low complexity architecture which can implement this JSICI scheme efficiently in VLSI. Also low power features are proposed