Optimising the implementation of a FFT-based multicarrier CDMA receiver

Implementation aspects of a multicarrier code division multiple access (MC-CDMA) receiver with software reconfigurable power consumption is discussed. This receiver allows the power consumption to be reduced at the expense of an increase in processing delay. This delay may be important in real time response applications such as voice communications but not in other applications such as downloading data and therefore the power consumption can be optimised to the traffic. Power reduction is achieved at the cost of increased receiver latency. The performance of MC-CDMA receivers is also briefly discussed at the end of the paper.