Design of 1 V switched-current cells in standard CMOS process

Author

Rout, Saroj ; Lee, Edward K F

Author_Institution

Dept. of Electr. Eng. & Comput. Eng., Iowa State Univ., Ames, IA, USA

Volume

2

fYear

2000

fDate

2000

Firstpage

421

Abstract

The minimum supply voltage for a typical switched-current (SI) cell can be shown to be greater than 2V_T+2V_DSsat approximately due to the fact that an additional voltage drop is required for the MOS switch, which is connected to the gate of the memory transistor. Thus, a minimum supply voltage of 1.5 V is usually required in a standard CMOS process. In this paper, an active switching scheme is proposed for designing SI cells. The minimum supply voltage is equal to V_T+2V_DSsat. As a result, 1 V SI cells that exhibit low charge injection errors can be achieved

Keywords

CMOS analogue integrated circuits; analogue processing circuits; integrated circuit design; low-power electronics; switched current circuits; 1 V; MOS switch; SI cells; active switching scheme; low charge injection errors; memory transistor; standard CMOS process; supply voltage; switched-current cells; voltage drop; Analog circuits; CMOS process; Circuit synthesis; Low voltage; MOS devices; MOSFETs; Power system reliability; Switches; Threshold voltage; Wireless communication;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on

Conference_Location

Geneva

Print_ISBN

0-7803-5482-6

Type

conf

DOI

10.1109/ISCAS.2000.856354

Filename

856354