A low-power 6-b integrating-pipeline hybrid analog-to-digital converter [Bluetooth transceiver applications]

Author

Diduck, Quentin ; Margala, Martin

Author_Institution

Electr. & Comput. Eng. Dept., Univ. ofRochester, Rochester, NY, USA

fYear

2003

fDate

17-20 Sept. 2003

Firstpage

337

Lastpage

340

Abstract

This paper presents a novel low-power 6 bit ADC architecture for Bluetooth transceivers. It utilizes sequentially staged 3-bit integrating converters with interleaved sample and hold circuits. The characteristics of this architecture as well as areas that could lead to even more efficient devices are discussed. The device consumes 5.88 mA of current, 14.7 mW of power at a sampling rate of 50 MSamples/s, has an INL and DNL of 0.3 and 0.5 LSB, SNR of 36.6 dB, THD of 43.75 dB, and SFDR of 47.98 dB. Our architecture represents a 3.8 times improvement in power consumption, or a sampling rate with higher precision, compared to previously reported 6 bit implementations. An experimental prototype was simulated in 0.25 μm CMOS, with a supply voltage of 2.5 V.

Keywords

Bluetooth; CMOS integrated circuits; analogue-digital conversion; circuit simulation; integrated circuit design; low-power electronics; pipeline processing; sample and hold circuits; transceivers; 0.25 micron; 14.7 mW; 2.5 V; 5.88 mA; Bluetooth transceivers; CMOS; hybrid analog-to-digital converter; integrating-pipeline ADC; interleaved sample and hold circuits; low-power ADC; power consumption reduction; sampling rate precision; sequentially staged integrating converters; Analog-digital conversion; Bluetooth; Computer architecture; Counting circuits; Delay; Energy consumption; Mobile communication; Sampling methods; Transceivers; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

SOC Conference, 2003. Proceedings. IEEE International [Systems-on-Chip]

Print_ISBN

0-7803-8182-3

Type

conf

DOI

10.1109/SOC.2003.1241538

Filename

1241538