Title :
Energy and timing characterization of VLSI charge-pump phase-locked loops
Author :
Duarte, D. ; Vijaykrishnan, N. ; Irwin, M.J.
Author_Institution :
Microsyst. Design Lab., Pennsylvania State Univ., USA
Abstract :
Phased locked loops (PLLs) are frequently employed in high-speed communication links, RF demodulation systems and SOCs for frequency synthesis. As wireless portable systems become standard, performance and power PLL models are essential in order to explore design trade-offs and feasible power reductions. We present a PLL timing model, review results of our power model and couple them with expressions for jitter estimation. The model has been validated and shown to be within 5% of circuit level simulation numbers.
Keywords :
VLSI; circuit simulation; integrated circuit modelling; jitter; phase locked loops; timing; PLL power modeling; PLL timing model; RF demodulation systems; SOC; VLSI PLL timing characterization; charge-pump phase-locked loops; frequency synthesis; high-speed communication links; jitter estimation; wireless portable systems; Charge pumps; Circuit simulation; Coupling circuits; Demodulation; Frequency synthesizers; Phase locked loops; Power system modeling; Radio frequency; Timing jitter; Very large scale integration;
Conference_Titel :
SOC Conference, 2003. Proceedings. IEEE International [Systems-on-Chip]
Print_ISBN :
0-7803-8182-3
DOI :
10.1109/SOC.2003.1241539
