Self-timed ring architecture for SOC applications

This paper describes a modular deadlock-free ring bus architecture aimed for high-performance globally asynchronous locally synchronous SoC designs. The pipelined ring structure consists of consecutive bidirectional bus segments which can all operate in parallel. These segments are asynchronous point-to-point interconnects separated by identical self-timed transfer stages. Each system module accesses the ring via a transfer stage, and bus arbitration and control is distributed among the stages. According to simulations, using a 0.18 μm technology, the overall maximum performance varied between 4.9 and 6.6 Gword/s depending on the communication pattern and the ring topology.