Dual-mode convolutional/SOVA based turbo code decoder VLSI design for wireless communication systems

Author

Chen, Pen-Hsin ; Kai-Huang ; Hsueh, Nai-Hsuan ; Wu, An-Yeu

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

fYear

2003

fDate

17-20 Sept. 2003

Firstpage

369

Lastpage

372

Abstract

A prototype design of a dual-mode convolutional/turbo code decoder for 3^rd generation wireless communication systems is proposed. By merging some similar modules exist in the convolutional code and turbo code decoder, we build one dual-mode decoder with these two functions. Besides, in order to conform to the CDMA2000 standard, the architecture can also perform as a reconfigurable Viterbi decoder. It means that our decoder meets the multi code rate and multi generator polynomial convolutional code specification. The final prototyping chip is presented with Avant! 0.35 μm standard cell library.

Keywords

3G mobile communication; VLSI; Viterbi decoding; convolutional codes; integrated circuit design; turbo codes; 0.35 micron; 3G wireless communication systems; CDMA2000 standard; VLSI design; convolutional/SOVA based turbo code decoder; dual-mode decoder; multi code rate specification; multi generator polynomial convolutional code specification; reconfigurable Viterbi decoder; soft output Viterbi algorithm; Communication standards; Control systems; Convolution; Convolutional codes; Decoding; Hardware; Prototypes; Turbo codes; Very large scale integration; Wireless communication;

fLanguage

English

Publisher

ieee

Conference_Titel

SOC Conference, 2003. Proceedings. IEEE International [Systems-on-Chip]

Print_ISBN

0-7803-8182-3

Type

conf

DOI

10.1109/SOC.2003.1241545

Filename

1241545