Efficient VLSI design of a pulse shaping filter and DAC interface for W-CDMA transmission

Author

Berenguer, Inaki ; Palazzi, M. ; Bastidas-garcia, Oscar ; Bonizec, Loic ; Rasse, Yves

Author_Institution

Dept. of Electr. Eng., Columbia Univ., New York, NY, USA

fYear

2003

fDate

17-20 Sept. 2003

Firstpage

373

Lastpage

376

Abstract

This paper presents the design and VLSI implementation of a pulse shaping filter architecture for FDD W-CDMA transmission satisfying 3GPP specifications. We first study a filter design method to find the minimum number of coefficients and bits per coefficients to achieve the 3GPP requirements. Then, we propose a multiplierless linear phase FIR filter architecture implemented with an oversampling factor of four and minimizing size and power consumption. Design and requirements of the postfiltering elements and DAC interface are also defined. The implementation has been tested with an overall baseband transmission chain and results concerning the hardware complexity are given.

Keywords

3G mobile communication; FIR filters; VLSI; code division multiple access; digital-analogue conversion; integrated circuit design; linear phase filters; low-power electronics; pulse shaping circuits; 3GPP specifications; DAC interface; FDD W-CDMA transmission; FIR filter; VLSI; filter coefficients; filter oversampling factor; low-power design; multiplierless linear phase filter; postfiltering elements; pulse shaping filter; square root raised cosine filters; Design methodology; Energy consumption; Finite impulse response filter; Hardware; Matched filters; Multiaccess communication; Pulse shaping methods; Telephone sets; Transmitters; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

SOC Conference, 2003. Proceedings. IEEE International [Systems-on-Chip]

Print_ISBN

0-7803-8182-3

Type

conf

DOI

10.1109/SOC.2003.1241546

Filename

1241546