New trends in low power SoC design technologies

Summary form only given. The growing complexity of system-on-chip (SoC) continues to advance the concept of low power devices/circuits/architectures/algorithms co-design. This requires the close interaction among various disciplines to be involved in the development of low power high performance computer, communication and consumer SoC applications. The design of low power wireless mobile SoC products now must equally concern itself with digital and analog mixed-signal devices and circuits, interconnection wires and nano-scale CMOS technology. The reduction of the power consumption in low voltage circuits is necessary to reduce the leakage power in both the active and standby modes of operation. The reduction in leakage current in design has to be achieved using circuit-level and physical-layout techniques. This tutorial paper first considers major circuit techniques and then considers physical-layout techniques for leakage control and reduction. This paper also considers voltage island techniques, concurrent mixed-signal semi-custom design methodology, dual-supply techniques for regular logic fabric VPGA and cache memory, system-level power management, and silicon-implementation platform design.