Partial Reconfiguration Applied in an On-line Evolvable Pattern Recognition System

One of the main challenges with autonomous adaptable systems is the lack of hardware flexibility. However, reconfigurable logic is a promising technology for run-time adaptable systems ¿ often called reconfigurable computing. The paper outlines how reconfiguration can be applied at run-time for an on-line evolvable system to improve flexibility in the hardware. The challenge of the latter is to include flexibility without resynthesis and avoid having a too large logic gate overhead. An architecture based on system-on-chip and partial reconfiguration is presented in the paper. Results from implementation show that reconfiguration can be undertaken in a few milliseconds for one category detection module of our classification system.