VLSI implementation of Gm-C filter using modified Nauta OTA with double CMOS pair

In the literature, a modified Nauta´s OTA has been proposed for achieving higher PSRR and CMRR. In this paper, a modified Nauta´s OTA with double CMOS pair is proposed and is used for implementing a programmable Gm-C filter. The double CMOS pair enables the transconductance to be varied by varying the bias voltages at high impedance nodes. This in turn results in programmability of the filter (F-tuning). For the purpose of comparison, the proposed OTA and Nauta´s OTA reported in the literature are implemented in UMC-0.18μm CMOS process and studied through simulation. The proposed OTA results in 11 dB increase in the PSRR and 21 dB increase in the CMRR compared to the Nauta´s OTA. The tunable second order Gm-C band pass filter using the proposed OTA is implemented and studied. Simulation of filter is done with BSIM3V3 parameters under (±0.9V) supply voltage and (±1.4V) supply voltage for biasing of double CMOS pair. It is verified from the post-layout simulation that the filter can be tuned over the range (10MHz-300MHz).