New metrics for architectural level power performance evaluation

In this paper, we present new metrics to evaluate the performance of VLSI circuits with regards to the power consumption in the architectural level from the system point of view. One advantage of the new metrics is that the metrics not only calculate the power consumption itself but also evaluate the “low power possibility” of the architectures from the system point of view; another advantage is that the metrics consider the effects of the process technology and it can be used to evaluate the power consumption performance in the future advanced VLSI technology. Specially, we point out that reducing power supply voltage to reduce the power consumption will become less and less efficient in the deep submicron regime and thus the architecture-driven voltage scaling low power design approach will not work as well as in the previous technology