Design and implementation of high performance dynamic 64-bit parallel adder with enhanced testability

Author

Hwang, W. ; Gristede, G.D. ; Sanda, P.N. ; Wang, S.Y. ; Heidel, D.F.

Author_Institution

IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

fYear

1998

fDate

11-14 May 1998

Firstpage

519

Lastpage

522

Abstract

This paper presents a fast, low power, binary carry look-ahead 64-bit dynamic parallel adder architecture for a high frequency microprocessor. The adder core is composed of several basic building blocks and feedback reset chain blocks implemented in self-resetting CMOS (SRCMOS) circuits. All circuits are design with enhanced testability. A new tool, SPA (SRCMOS Pulse Analyzer) is developed for dynamic and static checks. The nominal propagation delay and power dissipation of the adder are measured to be 1.5 ns (at 22 C with Vdd=2.5 V) and 300 mW. The adder core size is 1.6 mm×0.275 mm. The process that the design is based upon in a 0.5 μm IBM CMOS5X technology with 0.25 μm effective channel length and 5 layers of metal. The circuit techniques are ready to be migrated to sub-nanosecond microprocessor design

Keywords

CMOS logic circuits; adders; carry logic; circuit feedback; design for testability; parallel architectures; 0.25 micron; 0.5 micron; 1.5 ns; 2.5 V; 300 mW; 64 bit; IBM CMOS5X technology; SPA tool; SRCMOS Pulse Analyzer; adder architecture; carry look-ahead adder; dynamic parallel adder; feedback reset chain blocks; high frequency microprocessor application; low power operation; self-resetting CMOS circuits; testability; Adders; CMOS technology; Circuit testing; Feedback circuits; Frequency; Microprocessors; Power dissipation; Power measurement; Process design; Propagation delay;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1998. Proceedings of the IEEE 1998

Conference_Location

Santa Clara, CA

Print_ISBN

0-7803-4292-5

Type

conf

DOI

10.1109/CICC.1998.695032

Filename

695032