Title :
A 5.5 GHz prescaler in 0.18 μm CMOS technology
Author :
Ajjikuttira, Aruna B. ; Chan, Wei Liat ; Lian, Yong
Author_Institution :
Inst. of Microelectron., Singapore, Singapore
Abstract :
A high-speed dual-modulus divide-by-32/33 prescaler (DMP) has been fabricated in a standard 0.18 μm CMOS process. It consists of a divide-by-4/5 synchronous divider implemented in MOS current-mode logic and a divide-by-8 asynchronous counter realized in differential cascode voltage-switch logic. A fully differential architecture is adopted, which offers immunity against noise, fabrication process and supply voltage variation. The measured operating frequency range is from 4.6 to 6.2 GHz, making it suitable for WLAN applications. Including the buffers, the circuit draws about 29 mA from a 1.8 V power supply and occupies less than 1 mm2 die area.
Keywords :
CMOS logic circuits; asynchronous circuits; buffer circuits; current-mode logic; dividing circuits; low-power electronics; prescalers; wireless LAN; 0.18 micron; 1.8 V; 29 mA; 4.6 to 6.2 GHz; 5.5 GHz; CMOS; MOS current-mode logic; WLAN; differential cascode voltage-switch logic; divide-by-4/5 synchronous divider; divide-by-8 asynchronous counter; dual-modulus divide-by-32/33 prescaler; fully differential architecture; operating frequency range; supply voltage variation; CMOS logic circuits; CMOS process; CMOS technology; Circuit noise; Counting circuits; Fabrication; Frequency measurement; Power supplies; Voltage; Wireless LAN;
Conference_Titel :
ASIC, 2002. Proceedings. 2002 IEEE Asia-Pacific Conference on
Print_ISBN :
0-7803-7363-4
DOI :
10.1109/APASIC.2002.1031534
