Layout design and verification for cell library to improve ESD/latchup reliability in deep-submicron CMOS technology

A methodology to verify the ESD and latchup reliability of CMOS cell libraries has been proposed. The ESD- or latchup-sensitive layout in the cell library can be found by this proposed methodology with DRC (design rules check) and ERC (electrical rules check), before the chip is fabricated. By changing the layout in the suggested way of high immunity to ESD and latchup without increasing the layout area of the internal cores, the ESD and latchup reliability of CMOS IC´s assembled by the verified cell library can be significantly improved without trial-and-error design modification and wafer fabrication