Title :
Novel cascode NCLSCR/PCLSCR design with tunable holding voltage for safe whole-chip ESD protection
Author :
Ker, Ming-Dou ; Chang, Hun-Hsien
Author_Institution :
Dept. of IC Product Eng., Ind. Technol. Res. Inst., Hsinchu, Taiwan
Abstract :
A novel design has been proposed to safely apply the NCLSCR (NMOS-controlled lateral SCR) and PCLSCR (PMOS-controlled lateral SCR) devices for whole-chip ESD (electrostatic discharge) protection in CMOS ICs without causing the unexpected operation errors or the VDD-to-VSS latchup issue. By using the cascode configuration, the ESD protection circuit with the cascode NCLSCRs or PCLSCRs has a tunable holding voltage greater than VDD of the ICs. Such cascode NCLSCRs (or PCLSCRs) can provide the CMOS IC´s with effective ESD protection but without accidentally triggering on by the overshooting (under-shooting) noise pulses in the system applications. This novel cascode NCLSCRs (PCLSCRs) design has been practically applied to protect the ICs in a 0.35 μm silicide CMOS technology with the HBM ESD robustness above 3 kV
Keywords :
CMOS integrated circuits; electrostatic discharge; integrated circuit design; protection; thyristor applications; 0.35 micron; 3 kV; ESD protection circuit; NMOS-controlled lateral SCR devices; PMOS-controlled lateral SCR devices; cascode NCLSCR/PCLSCR design; electrostatic discharge protection; overshooting noise pulses; submicron CMOS IC; tunable holding voltage; under-shooting noise pulses; whole-chip ESD protection; Application specific integrated circuits; CMOS integrated circuits; CMOS technology; Circuit noise; Electrostatic discharge; Integrated circuit noise; Protection; Thyristors; Tunable circuits and devices; Voltage;
Conference_Titel :
Custom Integrated Circuits Conference, 1998. Proceedings of the IEEE 1998
Conference_Location :
Santa Clara, CA
Print_ISBN :
0-7803-4292-5
DOI :
10.1109/CICC.1998.695036
