Title :
Simultaneous switching noise analysis and low bouncing buffer design [CMOS ICs]
Author :
Jou, Shyh-Jye ; Cheng, Wei-Chung ; Lin, Yu-Tao
Author_Institution :
Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan
Abstract :
An accurate equation to estimate Simultaneous Switching Noise (SSN) in CMOS integrated circuits including the carrier velocity saturation effects of the short-channel MOSFET is proposed. Simulation results show that the proposed close-form equation estimates the SSN precisely and the error is below 5% as compared with HSPICE simulation results. Design procedures of low bouncing tapered buffer that take SSN into consideration are also proposed. Finally, several output buffer design examples are implemented to verify the low bouncing buffer design
Keywords :
CMOS integrated circuits; buffer circuits; integrated circuit design; integrated circuit noise; CMOS integrated circuits; carrier velocity saturation effects; close-form equation; low bouncing buffer design; short-channel MOSFET; simultaneous switching noise analysis; submicron CMOS; tapered buffer; Bonding; Delay effects; Driver circuits; Equations; Inductance; Integrated circuit noise; MOSFET circuits; Signal design; Switches; Voltage;
Conference_Titel :
Custom Integrated Circuits Conference, 1998. Proceedings of the IEEE 1998
Conference_Location :
Santa Clara, CA
Print_ISBN :
0-7803-4292-5
DOI :
10.1109/CICC.1998.695037
