Evaluation of power consumption in adiabatic circuits

In this paper a simple and accurate model to evaluate the energy consumption of the digital adiabatic circuits is proposed. It is based on a linearization of the circuit, which leads to an RC mesh equivalent circuit. The obtained expression of the energy consumption of a generic adiabatic gate is very simple, thus it can be used for pencil-and-paper calculations. The predicted values were compared to Spice results using a 0.8 μm CMOS technology. The average error is below 3.5%, and for practical switching frequencies the maximum error is always lower than 8%. Therefore, the proposed model can be also used to implement an accurate and efficient power simulator tool