Title :
Optimization techniques for maximum power-efficiency of deep sub-micron CMOS digital circuits
Author :
Kwok, Daniel SC ; Margala, Martin
Author_Institution :
Dept. of Electr. & Comput. Eng., Alberta Univ., Edmonton, Alta., Canada
Abstract :
This paper presents results of a study to locate the optimal operating power supply voltage for a maximum power-efficiency operation of CMOS digital circuits in a deep sub-micron environment. The results show that the optimal VDD is a strong function of NMOS and PMOS device threshold voltages and their sizes. Depending on the capacitive loading, the optimal VDD=ξ(|Vtp|+V tn), where ξ is (0.9-1.1). The study targets low-power low-voltage applications of digital pass-transistor circuits with multiple operating voltages. The analysis has been performed using BSIM Level 28 models and verified with HSPICE. The experimental circuits were designed in 0.35 μm CMOS technology
Keywords :
CMOS digital integrated circuits; circuit optimisation; integrated circuit design; integrated circuit modelling; logic design; low-power electronics; 0.35 micron; BSIM Level 28 models; HSPICE; NMOS device threshold voltage; PMOS device threshold voltage; capacitive loading; deep submicron CMOS digital circuits; digital pass-transistor circuits; low-power applications; low-voltage applications; maximum power efficiency; multiple operating voltages; optimal operating power supply voltage; optimization techniques; Batteries; CMOS digital integrated circuits; CMOS technology; Digital circuits; Equations; Logic; MOS devices; Power supplies; Propagation delay; Threshold voltage;
Conference_Titel :
Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on
Conference_Location :
Geneva
Print_ISBN :
0-7803-5482-6
DOI :
10.1109/ISCAS.2000.856409
