IP cores integration in DSP System-on-chip designs

Successful integration of IP/VC blocks requires a set of view that provides the appropriate information for each IP Block through the design flow for an IP-integration system. In this paper, we present a methodology of IP integration in a System-on a chip (SOC) design, that exploits both IP designer and SOC integrator constraints. First, we describe a method to extract and specify IP functional and timing constraints (I/O sequence transfer constraints) from the IP core. Second, we propose a modeling style of the integration constraints and a technique for merging them with IP constraints. This technique allows the specification and design of an optimized IP interface unit required for IP-Socketization. The synthesis output is synthesizable VHDL RT of the interface, a detailed Bus-Functional model of the IP core towards Cosimulation.