Title :
A CMOS low-IF programmable gain amplifier with speed-enhanced DC offset cancellation
Author :
Wang, Chao-Shiun ; Huang, Po-Chiun
Author_Institution :
SoC Technol. Center, Ind. Technol. Res. Inst., Hsinchu, Taiwan
Abstract :
This paper presents a programmable gain amplifier (PGA) for a dual band (GSM900/DCS1800) low-IF receiver. It uses a negative feedback approach to achieve the high linearity requirement. In addition to the amplifier, anti-alias filtering and DC offset removal are included for the subsequent IF signal processing. A dual-bandwidth algorithm is developed to speed up the settling time on DC removal. A modified Sallen-Key filter helps to provide better than 40 dB anti-aliasing and blocker attenuation near the sampling frequency of 13 MHz. The overall PGA gain varies from 0 dB to 46 dB with 2 dB per step. With a 0.25 μm CMOS process, this device dissipates 10.3 mW from a 2.7 V supply voltage.
Keywords :
CMOS integrated circuits; cellular radio; circuit CAD; circuit simulation; feedback amplifiers; integrated circuit design; integrated circuit modelling; intermediate-frequency amplifiers; programmable circuits; radiofrequency filters; radiotelephony; 0 to 46 dB; 0.25 micron; 10.3 mW; 13 MHz; 2.7 V; CMOS low-IF programmable gain amplifier; CMOS process; DC offset removal; GSM900/DCS1800 receivers; IF signal processing; PGA gain steps; PGA power dissipation/supply voltage; Sallen-Key filters; anti-alias filtering; anti-aliasing/blocker attenuation; dual band low-IF receivers; high linearity negative feedback technique; sampling frequency; settling time speed up dual-bandwidth algorithm; speed-enhanced DC offset cancellation; Attenuation; Dual band; Electronics packaging; Filtering; Filters; Frequency; Linearity; Negative feedback; Signal processing algorithms; Signal sampling;
Conference_Titel :
ASIC, 2002. Proceedings. 2002 IEEE Asia-Pacific Conference on
Print_ISBN :
0-7803-7363-4
DOI :
10.1109/APASIC.2002.1031550
