A 3.3 V-110 MHz 10-bit CMOS current-mode DAC

Author

Park, Sung Yong ; Cho, Hyun Ho ; Yoon, Kwang Sub

Author_Institution

Dept. of Electron. Eng., Inha Univ., Inchon, South Korea

fYear

2002

fDate

2002

Firstpage

173

Lastpage

176

Abstract

This paper describes a 3.3 V-110 MHz 10 bit CMOS current-mode digital to analog converter (DAC) weighting with a 6 MSB current matrix stage and a 4 LSB binary weighting stage. The linearity errors (INL/DNL) caused by random and system errors are reduced by the proposed 2D hierarchically symmetrical centroid sequencing methodology. A new deglitch circuit is proposed to minimize the glitch energy. The simulation shows a conversion rate of 110 MHz, INI/DNL of ±0.8 LSB/±0.5 LSB, a glitch energy of 3.5 pV·sec, and a power dissipation of 126 mW at 3.3 V.

Keywords

CMOS integrated circuits; current-mode circuits; digital-analogue conversion; low-power electronics; 10 bit; 110 MHz; 126 mW; 2D hierarchically symmetrical centroid sequencing methodology; 3.3 V; CMOS; INI/DNL; binary weighting stage; conversion rate; current matrix stage; current-mode DAC; deglitch circuit; glitch energy; linearity errors; power dissipation; system errors; Analog-digital conversion; CMOS technology; Circuit simulation; Impedance; Linearity; Matrix converters; Power dissipation; Power engineering and energy; Symmetric matrices; Transconductance;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2002. Proceedings. 2002 IEEE Asia-Pacific Conference on

Print_ISBN

0-7803-7363-4

Type

conf

DOI

10.1109/APASIC.2002.1031560

Filename

1031560