A 1 V CMOS analog comparator using auto-zero and complementary differential-input technique

Author

Hung, Yu-Cherng ; Liu, Bin-Da

Author_Institution

Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan

fYear

2002

fDate

2002

Firstpage

181

Lastpage

184

Abstract

A CMOS comparator operating over a 1 V to 5 V supply range is presented. No special low-voltage technology is used for fabrication. An experimental chip was fabricated using a 0.5 μm 5 V CMOS double-poly double-metal technology. The chip area of the comparator was 230×160 μm². Measured results at 1 V supply voltage show a comparator response time of less than 4 μs for 10 mV precision. Static power consumptions at 1 V supply voltage including input/output pads for comparator is 1 μW.

Keywords

CMOS analogue integrated circuits; comparators (circuits); integrated circuit design; low-power electronics; 0.5 micron; 1 muW; 1 to 5 V; 4 mus; CMOS analog comparator; CMOS double-poly double-metal technology; LV comparator; auto-zero technique; complementary differential-input technique; high common-mode noise rejection; low voltage operation; rail-to-rail input; variable supply capability; CMOS technology; Capacitors; Energy consumption; Low voltage; Parasitic capacitance; Preamplifiers; Sampling methods; Semiconductor device measurement; Switches; Time measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2002. Proceedings. 2002 IEEE Asia-Pacific Conference on

Print_ISBN

0-7803-7363-4

Type

conf

DOI

10.1109/APASIC.2002.1031562

Filename

1031562