Title :
CMOS VCO-prescaler cell-based design for RF PLL frequency synthesizers
Author :
Ahmed, A. ; Sharaf, K. ; Haddara, H. ; Ragai, H.E.
Author_Institution :
Mentor Graphics, Cairo, Egypt
Abstract :
Cell-based design using a new D-latch is employed to design a VCO and prescaler for RF PLL frequency synthesizers using a standard 0.5 μm CMOS process and 3.3 V supply. The divide-by 64/65 dual-modulus prescaler has a maximum operating frequency of 1.6 GHz and dissipates 9 mW. The VCO is a single-stage ring oscillator with a maximum frequency of 2.2 GHz and consumes 20 mW. The VCO and prescaler combination operates at a maximum frequency of 1.6 GHz and consumes 56 mW
Keywords :
CMOS digital integrated circuits; frequency synthesizers; phase locked loops; prescalers; voltage-controlled oscillators; 0.5 micron; 1.6 to 2.2 GHz; 3.3 V; 9 to 56 mW; CMOS VCO-prescaler cell-based design; D-latch; RF PLL frequency synthesizers; dual-modulus prescaler; single-stage ring oscillator; CMOS process; Circuits; Delay; Frequency conversion; Frequency synthesizers; Latches; Phase locked loops; Radio frequency; Ring oscillators; Voltage-controlled oscillators;
Conference_Titel :
Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on
Conference_Location :
Geneva
Print_ISBN :
0-7803-5482-6
DOI :
10.1109/ISCAS.2000.856434
