The CMOS on-chip oscillator based on level tracking technique

Author

Chia-Yang Chang ; Chen, Po-Chang ; Yang, Ching-Yang ; Lee, Yang-Han

fYear

2002

fDate

2002

Firstpage

197

Lastpage

200

Abstract

In this paper, we propose the architecture of a CMOS fully integrated level-locked loop (LLL). A 455 kHz LLL without external reference signal achieves the target of 1 percent variation, and consumes 9 mW with 3.6 V power supply in a standard 0.5 μm CMOS process. The frequency-to-voltage converter (FVC) in the LLL, built upon the charge redistribution principle, can decrease the process variation. A programmable controller is developed to increase the frequency accuracy. The voltage-controlled oscillator (VCO) is based on differential delay cells in order to minimize the effect of the power supply and the substrate noise. According to the main circuits, operated at 1.8 V provided by a regulator, the output frequency is accurately for 455 kHz from 2.0 V to 3.6 V.

Keywords

CMOS integrated circuits; phase locked loops; programmable circuits; voltage-controlled oscillators; voltage-frequency convertors; 0.5 micron; 1.8 V; 2 to 3.6 V; 455 kHz; 9 mW; CMOS on-chip oscillator; VCO; charge redistribution principle; differential delay cells; frequency accuracy; frequency-to-voltage converter; integrated level-locked loop; programmable controller; voltage-controlled oscillator; CMOS process; Circuit noise; Delay effects; Frequency conversion; Power supplies; Programmable control; Regulators; Signal processing; Target tracking; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2002. Proceedings. 2002 IEEE Asia-Pacific Conference on

Print_ISBN

0-7803-7363-4

Type

conf

DOI

10.1109/APASIC.2002.1031566

Filename

1031566