Reusable embedded debugger for 32 bit RISC processor using the JTAG boundary scan architecture

Author

Jung, Dae-Young ; Kwak, Sung-Ho ; Lee, Moon-Key

Author_Institution

Dept. of Electr. Eng., Yonsei Univ., Seoul, South Korea

fYear

2002

fDate

2002

Firstpage

209

Lastpage

212

Abstract

The traditional debug tools for chip tests and software developments need huge investment and plenty of time. These problems can be overcome by an embedded debugger based the JTAG boundary scan architecture. Thus, the IEEE 1149.1 standard is adopted by ASIC designers for testability problems. We designed the RED (reusable embedded debugger) using the JTAG boundary scan architecture. The proposed debugger is applicable for not only chip test but also software debugging. Our debugger has an additional hardware module (EICEM: embedded ICE module) for more critical real-time debugging.

Keywords

IEEE standards; boundary scan testing; embedded systems; fault location; integrated circuit testing; microprocessor chips; program debugging; reduced instruction set computing; 32 bit; ASIC design; IEEE 1149.1 standard; JTAG boundary scan architecture; RISC processor; chip test; chip tests; debug tools; embedded ICE module; hardware module; investment; real-time debugging; reusable embedded debugger; software debugging; software developments; Circuits; Computer architecture; Costs; Hardware; Ice; Investments; Protocols; Reduced instruction set computing; Software debugging; Software testing;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2002. Proceedings. 2002 IEEE Asia-Pacific Conference on

Print_ISBN

0-7803-7363-4

Type

conf

DOI

10.1109/APASIC.2002.1031569

Filename

1031569