DocumentCode
2234178
Title
High-level synthesis for testability: a survey and perspective
Author
Wagner, Kenneth D. ; Dey, Sujit
Author_Institution
Synopsys Inc., Mountain View, CA, USA
fYear
1996
fDate
3-7 Jun, 1996
Firstpage
131
Lastpage
136
Abstract
We review behavioral and RTL test synthesis and synthesis for testability approaches that generate easily testable implementations. We also include an overview of high-level synthesis techniques to assist high-level ATPG
Keywords
high level synthesis; logic CAD; logic testing; RTL test synthesis; high-level ATPG; high-level synthesis; synthesis for testability; test synthesis; testability; Automatic test pattern generation; Automatic testing; Built-in self-test; Circuit synthesis; Circuit testing; Hardware design languages; High level synthesis; Logic testing; Permission; Resource management;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference Proceedings 1996, 33rd
Conference_Location
Las Vegas, NV
ISSN
0738-100X
Print_ISBN
0-7803-3294-6
Type
conf
DOI
10.1109/DAC.1996.545559
Filename
545559
Link To Document